Research Article
Multi-Softcore Architecture on FPGA
Table 1
Configurable parameters.
| | Parameters | Time | Values | Default value |
| | Number of PEs | Design | , > 0 | |
| | Size of PE local memory | Design | Limited by the FPGA surface | 5 KB |
| | Neighborhood network’s topology | Design and runtime | Mesh, Torus, and Xnet | Torus |
| | Global router communication mode | Runtime | PE-PE,
PE-Controller,
PE-I/O Peripheral, and
Controller-I/O Peripheral | PE-Controller |
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