Multi-Softcore Architecture on FPGA

Table 3

Global router interface.

In
pe_d_in	[k] [32 b]	PE data (32-bit data vector (length = number of PEs))
pe_a_in	[k] [32 b]	PE address (32-bit address vector (length = number of PEs))
pe_wr	[k] [1 b]	PE read/write (1-bit R/W vector (length = number of PEs))
Ctrl_d_in	[32 b]	Controller data (32 bits)
Ctrl_a_in	[32 b]	Controller address (32 bits)
Ctrl_wr	[1 b]	Controller read/write signal
Out
pe_d_out	[k] [32 b]	PE data out
pe_a_out	[k] [32 b]	PE address
Ctrl_d_out	[32 b]	Controller data out
Ctrl_a_out	[32 b]	Controller address out
I/O Peripherals
SRAM_d_out	[32 b]	SRAM data out
SRAM_a_out	[32 b]	SRAM address out
SDRAM_d_in	[32 b]	SDRAM data in
SDRAM_a_in	[32 b]	SDRAM address
Acc_d_in	[32 b]	HW accelerator data in
Acc_a_in	[32 b]	HW accelerator address in