High Efficiency Generalized Parallel Counters for Look-Up Table Based FPGAs

Table 1

Comparison of different GPCs.

GPCs	Previous mappings			Mappings based on proposed; heuristic (Xilinx)			Mappings based on proposed; heuristic (Altera)
	LUTs	Delay	Efficiency	LUTs	Delay	Efficiency	LUTs	Delay	Efficiency
GPCs from [9]
(3; 2)	1		1	1		1	1		1
(6; 3)	3		1	2	+ 2	1.5	2	+ 2	1.5
(1, 5; 3)	3		1	1	+ 2	3	1	+ 2	3
GPCs from [8]
(6; 3)	4	2 + + 4	0.75	2	+	1.5	2	+	1.5
(1, 5; 3)	3	+ 3	1	1	+	3	1	+	3
(2, 3; 3)	3	+ 3	0.67	1	+	2	0		—
(7; 3)	4	2 + + 4	1	2	+ +	2	2	+	2
(1, 6; 4)	4	2 + + 4	0.75	3	+ +	1	3	+ +	1
(3, 5; 4)	4	2 + + 4	1	2	+ +	2	2	+	2
(4, 4; 4)	4	2 + + 4	1	3	+ +	1.33	3	+ +	1.33
(5, 3; 4)	4	2 + + 4	1	3	+	1.33	2	+	2
(6, 2; 4)	4	2 + + 4	1	2	+ +	2	2	+	2
GPCs from [15]
(6; 3)	3	2 + + 3	1	2	+	1.5	2	+	1.5
(1, 5; 3)	2	+ 2	1.5	1	+	3	1	+	3
(2, 3; 3)	2	+ 2	1	1	+	2	0		—
(7; 3)	3	2 + + 3	1.33	2	+ +	2	2	+	2
(5, 3; 4)	3	2 + + 3	1.33	3	+	1.33	2	+	2
(6, 2; 4)	3	2 + + 3	1.33	2	2 + + 3	2	2	+	2
(5, 0, 6; 5)	4	+ 4	1.5	4	+ 4	1.5	4	+ 4	1.5
(1, 4, 1, 5; 5)	4	+ 4	1.5	2	+ 4	3	2	+ 4	3
(1, 4, 0, 6; 5)	4	+ 4	1.5	3	+ 4	2	3	+ 4	2
(2, 0, 4, 5; 5)	4	2 + + 4	1.5	4	2 + + 4	1.5	4	2 + + 4	1.5

Delay associated with LUT.
²Delay associated with routing.
³Delay associated with carry chain.