High Efficiency Generalized Parallel Counters for Look-Up Table Based FPGAs

Table 3

Performance comparison for proposed GPC-based filters and DSP, IP based filters.

Filter design	LUTs	Registers (pipelined)	DSP cores	Critical path (nS)	Throughput (pipelined) (MHz)	EOP (nJ)	ET (nJ/bit)
IP based	747	1883	0	14.701	303.366	0.765	0.003
DSP based	128	240	31	18.398	363.086	0.581	0.0022
Proposed (5, 3; 4)	732	1683	0	7.68	355.65	0.573	0.0022
Proposed (6, 2; 4)	716	1683	0	11.31	335.4	0.599	0.0023
Proposed (1, 4, 0, 6; 5)	693	1683	0	12.69	355.21	0.571	0.0022
Proposed (1, 4, 1, 5; 5)	672	1683	0	12.34	355.2	0.555	0.0021