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International Journal of Reconfigurable Computing
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International Journal of Reconfigurable Computing
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2015
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Article
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Fig 13
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Research Article
Low Latency Network-on-Chip Router Microarchitecture Using Request Masking Technique
Figure 13
Logic cost comparison for VCs number of 2 and 4 (ports number = 5, payload width = 32, and buffer width = 4).