Low Latency Network-on-Chip Router Microarchitecture Using Request Masking Technique

Table 3

Hardware utilization summary of one NoC router on Cyclone IV & Stratix IV Altrea FPGA.

4 VCs/4 flits per VC	EP4CE115			EP4SGX230
	Proposed NoC	CONNECT two-clock	CONNECT one-clock	Proposed NoC	CONNECT two-clock	CONNECT one-clock
Logic cells (LCs)	2,890 (2.5%)	5,934 (5.2%)	5,690 (5.0%)	2,722 (1.5%)	5,473 (3%)	5,570 (3%)
Memory blocks (M9K)	5 (1.2%)	—	—	5 (0.6%)	—	—
Maximum frequency	88 MHz	65 MHz	41 MHz	177 MHz	148 MHz	91 MHz