Optimization of Lookup Schemes for Flow-Based Packet Classification on FPGAs

Algorithm 3

Proposed optimization for incremental update in IND.

Require: Range bounds , , , , next available URID and ERID for all chunks

 (1)   for   to   do

 (2)    

 (3)    

     // update region and bound memories

 (4)    for   to   do

 (5)     

 (6)     

 (7)     

 (8)    end for

 (9)    for   to   do

 (10)   

 (11)   

 (12)   ,

 (13)  end for

 (14) end for