Optimization of Lookup Schemes for Flow-Based Packet Classification on FPGAs

<div><svg height="9.21094pt" id="M148" style="vertical-align:-0.2129908pt" version="1.1" viewbox="-0.0498162 -8.99795 11.5092 9.21094" width="11.5092pt" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink"><g transform="matrix(.0135,0,0,-0.0135,0,0)"><path d="M822 650H589L583 622C660 617 677 607 674 561C672 534 664 481 647 390L600 137H596L273 650H126L120 622C176 620 194 615 207 594C221 571 225 557 214 504L161 257C141 166 129 112 121 85C108 42 83 30 29 28L23 0H260L266 28C193 33 173 42 176 89C178 122 186 172 202 255L256 527H259L583 -8H612L690 390C708 481 720 535 728 558C744 603 756 619 816 622L822 650Z" id="g113-79"></path><glyph.data ascent="3473" descent="-2876" horiz-adv-x="839" vert-adv-y="839"></glyph.data></g></svg>-rule lookup: (a) UV-based by concurrent matching of rule bounds, (b) UR-based by reducing memory expansion through a binary tree, and (c) UR-based by full memory expansion.</div>

International Journal of Reconfigurable Computing

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Figure 8

Figure 8: Optimization of Lookup Schemes for Flow-Based Packet Classification on FPGAs 