Optimization of Lookup Schemes for Flow-Based Packet Classification on FPGAs

Table 2

for real rulesets.

Set	SrcIP[15:0]	SrcIP[31:16]	DstIP[15:0]	DstIP[31:16]	Prot[7:0]	SrcPT[15:0]	DstPT[15:0]
ACL1	96	5	177	78	5	1	141
FW1	55	14	67	9	6	14	44
IPC1	282	40	549	97	8	32	51