Optimization of Lookup Schemes for Flow-Based Packet Classification on FPGAs

Table 3

Comparison of considered lookup schemes.

Lookup scheme	Memory	Logic	Mem BW
Logic-based ERM (BV) [36]
(Optional) postencoding BV UR	—	—	—
IND, no stitching (UR)
(Optional) postencoding UR BV
IND, no stitching (BV)
IND, BV-based horizontal stitching (BV) [10]
IND, UR-based horizontal stitching (UR) [13]	+
IND, vertical stitching (UR) [43]
Binary search (UR) [16]
(Optional) postencoding UR BV
Binary search (BV)