Optimization of Lookup Schemes for Flow-Based Packet Classification on FPGAs

Table 4

Performance of IND, horizontal BV-stitching, and 2D-pipelined architecture on FPGA (, ).

	Rules
	256				512				1024
	M20K	LUTs	Regs	Mlps	M20K	LUTs	Regs	Mlps	M20K	LUTs	Regs	Mlps
16	14	260	108	589	26	533	216	592	52	1078	450	555
32	28	388	216	588	52	775	432	588	104	1543	900	514
128	105	1149	810	509	195	2280	1620	450	390	4627	3375	377