Research Article
Optimization of Lookup Schemes for Flow-Based Packet Classification on FPGAs
Table 5
Performance of ERM and 2D-pipelined architecture on FPGA (
,
).
| | Rules | 256 | 512 | 1024 | M20K | LUTs | Regs | Mlps | M20K | LUTs | Regs | Mlps | M20K | LUTs | Regs | Mlps |
| 16 | 0 | 7721 | 9984 | 437 | 0 | 15433 | 19968 | 467 | 0 | 31235 | 39899 | 392 | 32 | 0 | 15145 | 19712 | 453 | 0 | 30464 | 39351 | 384 | 0 | 60902 | 78775 | 352 | 128 | 0 | 34845 | 77791 | 321 | 0 | 69815 | 155871 | 336 | 0 | 139676 | 312031 | 320 |
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