Research Article
Optimization of Lookup Schemes for Flow-Based Packet Classification on FPGAs
Table 6
Performance of BS and pipelined architecture on FPGA (
).
| | Rules | 256 | 512 | 1024 | M20K | LUTs | Regs | Mlps | M20K | LUTs | Regs | Mlps | M20K | LUTs | Regs | Mlps |
| 16 | 8 | 179 | 1254 | 328 | 10 | 206 | 1463 | 320 | 13 | 235 | 1684 | 293 | 32 | 16 | 316 | 2038 | 246 | 19 | 361 | 2343 | 229 | 24 | 407 | 2660 | 245 | 128 | 32 | 1054 | 6742 | 191 | 39 | 1193 | 7623 | 172 | 53 | 1332 | 8516 | 174 |
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