Leakage Immune Modified Pass Transistor Based 8T SRAM Cell in Subthreshold Region

Table 1

Results of conventional and modified access transistors logic at 0.4 V supply in 45 nm technology.

Access transistor type	Enable		Enable
	EN = 1 for NMOS = 0 for PMOS		EN = 0 for NMOS = 1 for PMOS		Operation
	(ON condition)		(OFF condition)
	Input given at node (V)	Output at node (V)	Input at node (V)	Output at node (V)	Turn-on	Turn-off
N (MN5/MN6)	0.4	0.247	0.4	0.097	Proper	Degraded
P	0.4	0.400	0.4	0.350	Proper	Degraded
NP	0.4	0.400	0.4	0.400	Proper	Degraded
PP	0.4	0.400	0.4	0.361	Proper	Degraded
PN	0.4	0.400	0.4	0.000	Proper	Proper
NN	0.4	0.038	0.4	0.000	Degraded	Proper