Research Article
Core-Level Modeling and Frequency Prediction for DSP Applications on FPGAs
Table 1
Switch matrix (SM) delay of select FPGA families.
| | Virtex-4 | Virtex-6 | Virtex-7 | Stratix-II | Stratix-IV | Stratix-V |
| SM delay | 0.5 ns | 0.35 ns | 0.175 ns | 0.4 ns | 0.25 ns | 0.175 ns |
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