A Scalable Unsegmented Multiport Memory for FPGA-Based Systems

Figure 1

This XOR memory has 3 ports. and are part of the same port. Port controls the address of each BRAM’s read port in and each BRAM’s write port in . Writing to memory using port requires reading from BRAMs in (except the one in ) as well as writing to the BRAMs in . Reading from memory requires reading from all the BRAMs in . Because the same read port on the BRAMs is used for reading and writing to the memory, it is not possible to split port into a read-only port and a write-only port as it is with LVT.