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International Journal of Reconfigurable Computing
Volume 2015 (2015), Article ID 902925, 13 pages
Research Article

Using Genetic Algorithms for Hardware Core Placement and Mapping in NoC-Based Reconfigurable Systems

Department of Electronics Systems, School of Engineering, University of Sao Paulo, Avenida Prof. Luciano Gualberto, Trav. 3, 05508-900 Sao Paulo, SP, Brazil

Received 21 October 2014; Revised 24 December 2014; Accepted 26 December 2014

Academic Editor: Salvatore Pontarelli

Copyright © 2015 Jonas Gomes Filho et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


Mapping of cores has been an important activity in NoC-based system design aimed to find the best topological location onto the NoC, such that the metrics of interest can be greatly optimized. In the last years, partial reconfigurable systems (PRSs) have included Networks-on-Chips (NoCs) as their communication structure, adding complexity to the problem of mapping. Several works have proposed specific and robust NoC architectures for PRSs, forming indirect and irregular networks, in which cases the mapping and placement problems must be treated altogether. The placement deals with the physical positioning of those cores inside the reconfigurable device. Up to now, to the best of our knowledge, the mapping-placement problem for those kinds of architectures has not been addressed yet. In this work, the problem formalization for the design-time hardware core placement and mapping in PRS-NoCs is proposed and methodologies for solving it with genetic algorithms (GAs) are presented. Several GA crossovers and methodologies are compared for obtaining the best solution. Results have shown that best GA solution obtained, in average, communication costs with 4% of penalty when compared with global minimum cost, obtained in a semiexhaustive approach. In addition, the algorithm presents low execution times.