Comment on “High Efficiency Generalized Parallel Counters for Look-Up Table Based FPGAs”

Table 1

Corrected mapping results of GPCs in [1] when using Xilinx Virtex 5 FPGAs (corrected values are marked in bold).

GPC	Results claimed in [1]			Corrected results			Ref.	Best design from the literature
	LUTs	Delay	Efficiency	LUTs	Delay	Efficiency		LUTs	Delay	Efficiency
(1,5;3)	1		3	2		1.5	[2]	2		1.5
(2,3;3)	1		2	2		1	[2]	2		1
(1,6;4)	3		1	4		0.75	[4]	4		0.75
(3,5;4)	2		1	4		1	[4]	4		1
(4,4;4)	3		1.33	4		1	[4]	4		1
(6,2;4)	2		2	4		1	[2]	3		1.33
(1,4,1,5;5)	2		4	4		1.5	[2]	4		1.5
(1,4,0,6;5)	4		1.5	5		1.2	[2]	4		1.5