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International Journal of Reconfigurable Computing
Volume 2016 (2016), Article ID 3561317, 7 pages
Research Article

Modules for Pipelined Mixed Radix FFT Processors

Computer Science Department, National Technical University of Ukraine, Peremogy Avenue 37, Kiev 03056, Ukraine

Received 26 October 2015; Revised 2 January 2016; Accepted 5 January 2016

Academic Editor: Michael Hübner

Copyright © 2016 Anatolij Sergiyenko and Anastasia Serhienko. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


A set of soft IP cores for the Winograd -point fast Fourier transform (FFT) is considered. The cores are designed by the method of spatial SDF mapping into the hardware, which provides the minimized hardware volume at the cost of slowdown of the algorithm by times. Their clock frequency is equal to the data sampling frequency. The cores are intended for the high-speed pipelined FFT processors, which are implemented in FPGA.