Table of Contents Author Guidelines Submit a Manuscript
International Journal of Reconfigurable Computing
Volume 2016, Article ID 4592780, 10 pages
http://dx.doi.org/10.1155/2016/4592780
Research Article

An Accelerating Solution for -Body MOND Simulation with FPGA-SoC

Bo Peng,1,2 Tianqi Wang,1,2 Xi Jin,1,2 and Chuanjun Wang3,4,5

1Key Laboratory of Strongly Coupled Quantum Matter Physics, Chinese Academy of Sciences, School of Physical Sciences, University of Science and Technology of China, Hefei, Anhui 230026, China
2Hefei Branch Center of National ASIC Design Engineering Technology Research Center, Institute of Advanced Technology, University of Science and Technology of China, Hefei, Anhui 230600, China
3Yunnan Observatories, Chinese Academy of Sciences, Kunming 650216, China
4Key Laboratory for the Structure and Evolution of the Celestial Objects, Chinese Academy of Sciences, Kunming 650216, China
5University of Chinese Academy of Sciences, Beijing 100049, China

Received 21 December 2015; Accepted 17 May 2016

Academic Editor: Michael Hübner

Copyright © 2016 Bo Peng et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

As a modified-gravity proposal to handle the dark matter problem on galactic scales, Modified Newtonian Dynamics (MOND) has shown a great success. However, the -body MOND simulation is quite challenged by its computation complexity, which appeals to acceleration of the simulation calculation. In this paper, we present a highly integrated accelerating solution for -body MOND simulations. By using the FPGA-SoC, which integrates both FPGA and SoC (system on chip) in one chip, our solution exhibits potentials for better performance, higher integration, and lower power consumption. To handle the calculation bottleneck of potential summation, on one hand, we develop a strategy to simplify the pipeline, in which the square calculation task is conducted by the DSP48E1 of Xilinx 7 series FPGAs, so as to reduce the logic resource utilization of each pipeline; on the other hand, advantages of particle-mesh scheme are taken to overcome the bottleneck on bandwidth. Our experiment results show that 2 more pipelines can be integrated in Zynq-7020 FPGA-SoC with the simplified pipeline, and the bandwidth requirement is reduced significantly. Furthermore, our accelerating solution has a full range of advantages over different processors. Compared with GPU, our work is about 10 times better in performance per watt and 50% better in performance per cost.