How to Efficiently Reconfigure Tunable Lookup Tables for Dynamic Circuit Specialization

Table 8

Maximum clock the design can support on the Zynq-SoC.

	16-tap FIR	32-tap FIR	64-tap FIR
Number of TLUTs to be clustered	384	768	1536
Clock frequency in MHz	108.6/102.8	108.6/102.2	108.6/101.2

Note: the above values are in the form without placement constraints/with placement constraints.