FPGA Based High Speed SPA Resistant Elliptic Curve Scalar Multiplier Architecture

Table 4

Clock cycles requirements for different designs.

Design	Field size	Point addition	Point doubling	EC point multiplication
This work	160	437	495	79,200
	192	523	591	113,472
[21]	160		814	130,240
	192		974	187,008
[25]	160	868	668	153,000
[18]	160	809	972	283,000
[24]	167	2120	2540	545,040
[26]	192	—	—	300,000
[22]	192	—	—	120,000