International Journal of Reconfigurable Computing / 2016 / Article / Tab 4

Research Article

FPGA Based High Speed SPA Resistant Elliptic Curve Scalar Multiplier Architecture

Table 4

Clock cycles requirements for different designs.

DesignField sizePoint additionPoint doublingEC point multiplication

This work160437495 79,200
192523591113,472

[21] 160814130,240
192974187,008

[25]160868668153,000
[18]160809972283,000
[24]16721202540545,040
[26]192300,000
[22]192120,000

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