An Efficient Evolutionary Task Scheduling/Binding Framework for Reconfigurable Systems

Table 10

Resources utilization for the system on a Virtex-V FPGA (XC5VFX70T), freq. 100 MHz.

Resources	Utilization	Available	Utilization %
Register	12022	44800	26
LUT	11176	44800	24
Slice	6282	11200	56
IO	237	640	37
BSCAN	1	4	25
BUFIO	8	80	10
DCM_ADV	1	12	8
DSP48E	6	128	4
ICAP	1	2	50
Global clock buffer	6	32	18