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International Journal of Reconfigurable Computing
Volume 2017, Article ID 2410408, 12 pages
Research Article

Efficient Realization of BCD Multipliers Using FPGAs

1Department of Electrical and Computer Engineering, Royal Military College of Canada, Kingston, ON, Canada
2Department of Computer Engineering, École Polytechnique de Montréal, Montréal, QC, Canada

Correspondence should be addressed to Dhamin Al-Khalili; ac.cmr@d-ililahkla

Received 22 October 2016; Revised 2 February 2017; Accepted 9 February 2017; Published 6 March 2017

Academic Editor: Seda Ogrenci-Memik

Copyright © 2017 Shuli Gao et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Citations to this Article [3 citations]

The following is the list of published articles that have cited the current article.

  • Mário Véstias, and Horácio Neto, “Improving the area of fast parallel decimal multipliers,” Microprocessors and Microsystems, vol. 61, pp. 96–107, 2018. View at Publisher · View at Google Scholar
  • Mubin Ul Haque, Zarrin Tasnim Sworna, Hafiz Md. Hasan Babu, and Ashis Kumer Biswas, “A Fast FPGA-Based BCD Adder,” Circuits, Systems, and Signal Processing, 2018. View at Publisher · View at Google Scholar
  • Sasidhar Mukkamala, Pradeep Rathore, and Rangababu Peesapati, “Decimal multiplication using compressor based-BCD to binary converter,” Engineering Science and Technology, an International Journal, 2018. View at Publisher · View at Google Scholar