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International Journal of Reconfigurable Computing
Volume 2017 (2017), Article ID 2410408, 12 pages
https://doi.org/10.1155/2017/2410408
Research Article

Efficient Realization of BCD Multipliers Using FPGAs

Shuli Gao,1 Dhamin Al-Khalili,1 J. M. Pierre Langlois,2 and Noureddine Chabini1

1Department of Electrical and Computer Engineering, Royal Military College of Canada, Kingston, ON, Canada
2Department of Computer Engineering, École Polytechnique de Montréal, Montréal, QC, Canada

Correspondence should be addressed to Dhamin Al-Khalili; ac.cmr@d-ililahkla

Received 22 October 2016; Revised 2 February 2017; Accepted 9 February 2017; Published 6 March 2017

Academic Editor: Seda Ogrenci-Memik

Copyright © 2017 Shuli Gao et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

How to Cite this Article

Shuli Gao, Dhamin Al-Khalili, J. M. Pierre Langlois, and Noureddine Chabini, “Efficient Realization of BCD Multipliers Using FPGAs,” International Journal of Reconfigurable Computing, vol. 2017, Article ID 2410408, 12 pages, 2017. doi:10.1155/2017/2410408