Efficient Realization of BCD Multipliers Using FPGAs

<table class="figure-group"><tr class="fig-image" id="a"><td><object data="https://static.hindawi.com/articles/ijrc/volume-2017/2410408/figures/2410408.fig.007a.svgz" name="2410408.fig.007a" type="image/svg+xml"></object></td></tr><tr class="fig-caption"><td><b>(a) </b>Triangular organization</td></tr><tr class="fig-image" id="b"><td><object data="https://static.hindawi.com/articles/ijrc/volume-2017/2410408/figures/2410408.fig.007b.svgz" name="2410408.fig.007b" type="image/svg+xml"></object></td></tr><tr class="fig-caption"><td><b>(b) </b>Two groups of the partial products</td></tr></table>

<div>A 4 × 4-digit BCD multiplier.</div>

International Journal of Reconfigurable Computing

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Figure 7

Figure 7: Efficient Realization of BCD Multipliers Using FPGAs 