Efficient Realization of BCD Multipliers Using FPGAs

Table 1

Final correction for the BCD adder.

		= 1	Comments
	0 0 0 0	0 0 0 0		0 0 0 1	“+3” is not required
0 0 0 1	0 0 0 1	0 0 1 0	“+3” is not required
0 0 1 0	0 0 1 0	0 0 1 1	“+3” is not required
0 0 1 1	0 0 1 1	0 1 0 0	“+3” is not required
0 1 0 0	0 1 0 0	1 0 0 0	at C0 = 1, “+3” is required
0 1 0 1	x x x x	x x x x
0 1 1 0	x x x x	x x x x
0 1 1 1	x x x x	x x x x
1 0 0 0	1 0 0 0	1 0 0 1	“+3” has been performed
1 0 0 1	1 0 0 1	1 0 1 0	“+3” has been performed
1 0 1 0	1 0 1 0	1 0 1 1	“+3” has been performed
1 0 1 1	1 0 1 1	1 1 0 0	“+3” has been performed
1 1 0 0	x x x x	x x x x
1 1 0 1	x x x x	x x x x
1 1 1 0	x x x x	x x x x
1 1 1 1	x x x x	x x x x