Efficient Realization of BCD Multipliers Using FPGAs

Table 3

Results compared with [22] for the 16 × 16-digit pipelined multiplier.

# of pipeline; stages	[22]			Proposed			Comparison
	Total delay (ns)	Clock cycle (ns)	#LUTs	Total delay (ns)	Clock cycle (ns)	#LUTs	Delay reduction (%)	Clock cycle time reduction (ns)	# of LUT saving (%)
5	27.400	5.480	6438	19.025	3.805	6843	30.57	30.57	−6.29
6	28.740	4.830	6664	22.242	3.707	6918	22.61	23.25	−3.81
7	30.660	4.460	5992	28.392	4.056	6953	7.40	9.06	−16.04