FPGA-Based Channel Coding Architectures for 5G Wireless Using High-Level Synthesis

Figure 5

Throughput improvement using access pattern analysis. Shown on (a) is the representative schematic of the LabVIEW graphical programming virtual instrument (VI), and on (b and c) are the corresponding timing diagrams.

(a) Algorithm description (application diagram)

(b) Without access pattern analysis

(c) With access pattern analysis