-- FmReceiver library package
use work.SdrHlsPkg.all;
--FmReceiver top level entity
entity FmReceiver is
port(
...
);
end FmReceiver;
architecture rtl of FmReceiver is
-- declare registers
...
begin
-- instantiate adc component
FMC150Inst: FMC150
port map();
-- instantiate adc to ddcfifo channel
FMC150Inst_DDCInst_Channel1: sdf_channel
generic map(
DATA_BITS  =>  32,  DEPTH  =>  2,  PRD_RATE  =>  1,  CNS_RATE  =>  1,  INIT_DLY  =>  0)
port map();
-- instantiate ddc component
DDInst: ddc
generic map(
DIN_WIDTH  =>  16,  DOUT_WIDTH  =>  16,...)
port map();
-- instantiate ddc to Gbe fifo channel
DDCInst_UDP1GbEIns_Channel2: sdf_channel
generic map(
DATA_BITS  =>  32,  DEPTH  =>  18,  PRD_RATE  =>  1,  CNS_RATE  =>  16,  INIT_DLY  =>  0)
port map();
-- instantiate Gigabit Ethernet
UDP1GbEIns: UDP1GbE
generic map(TX_BYTES => 64, RX_BYTES => 0)
port map();
end rtl;
Listing 3: VHDL source code for the FM Receiver.