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International Journal of Reconfigurable Computing
Volume 2017 (2017), Article ID 5419767, 17 pages
Research Article

A High-Level Synthesis Scheduling and Binding Heuristic for FPGA Fault Tolerance

1Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL 32611, USA
2National Instruments Corp., 11500 N Mopac Expwy, Austin, TX 78759, USA

Correspondence should be addressed to David Wilson

Received 31 March 2017; Revised 2 July 2017; Accepted 11 July 2017; Published 21 August 2017

Academic Editor: Michael Hübner

Copyright © 2017 David Wilson et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


Computing systems with field-programmable gate arrays (FPGAs) often achieve fault tolerance in high-energy radiation environments via triple-modular redundancy (TMR) and configuration scrubbing. Although effective, TMR suffers from a 3x area overhead, which can be prohibitive for many embedded usage scenarios. Furthermore, this overhead is often worsened because TMR often has to be applied to existing register-transfer-level (RTL) code that designers created without considering the triplicated resource requirements. Although a designer could redesign the RTL code to reduce resources, modifying RTL schedules and resource allocations is a time-consuming and error-prone process. In this paper, we present a more transparent high-level synthesis approach that uses scheduling and binding to provide attractive tradeoffs between area, performance, and redundancy, while focusing on FPGA implementation considerations, such as resource realization costs, to produce more efficient architectures. Compared to TMR applied to existing RTL, our approach shows resource savings up to 80% with average resource savings of 34% and an average clock degradation of 6%. Compared to the previous approach, our approach shows resource savings up to 74% with average resource savings of 19% and an average heuristic execution time improvement of 96x.