Research Article
A High-Level Synthesis Scheduling and Binding Heuristic for FPGA Fault Tolerance
Input: Operator assignments to control-steps, | Output: Operator bindings to resources, | begin | Stage 1 Binding | ; | foreach module do | LeftEdgeAlgorithm | end | Stage 2 Binding | shares ; | limit GetLimit ; | singleton, non-singleton SeparateRes ; | Stage 2: Merge singletons with non-singletons | foreach resource of singleton do | foreach resource of non-singleton do | if shares = limit then break; | ; | if IsMergeable then | add operator of to and remove from singleton; | shares shares + 1; | end | end | end | Stage 2: Merge singletons with other singletons | foreach pair of singleton do | if shares = limit then break; | ; | if IsMergeable then | add operator of to and remove and from singleton; | add to non-singleton; | shares shares + 1; | end | end | singleton non-singleton; | return | end |
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