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International Journal of Reconfigurable Computing
Volume 2017, Article ID 5419767, 17 pages
https://doi.org/10.1155/2017/5419767
Research Article

A High-Level Synthesis Scheduling and Binding Heuristic for FPGA Fault Tolerance

1Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL 32611, USA
2National Instruments Corp., 11500 N Mopac Expwy, Austin, TX 78759, USA

Correspondence should be addressed to David Wilson; ude.lfu@nosliw.d

Received 31 March 2017; Revised 2 July 2017; Accepted 11 July 2017; Published 21 August 2017

Academic Editor: Michael Hübner

Copyright © 2017 David Wilson et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

How to Cite this Article

David Wilson, Aniruddha Shastri, and Greg Stitt, “A High-Level Synthesis Scheduling and Binding Heuristic for FPGA Fault Tolerance,” International Journal of Reconfigurable Computing, vol. 2017, Article ID 5419767, 17 pages, 2017. https://doi.org/10.1155/2017/5419767.