A High-Level Synthesis Scheduling and Binding Heuristic for FPGA Fault Tolerance

Table 2

Resource savings (LUT%) of FD-FTA heuristic compared to TMR-RTL for 100% and 70% EC.

Benchmark	Normalized latency and EC% constraints
	1.0x		1.2x		1.4x		1.6x		1.8x		2.0x
	100%	70%	100%	70%	100%	70%	100%	70%	100%	70%	100%	70%
lapjacobi	0%	0%	0%	0%	5%	30%	2%	5%	2%	2%	5%	4%
lapsor	0%	0%	−1%	−1%	−1%	−1%	−1%	2%	−2%	0%	−2%	0%
conv5x5	18%	18%	52%	52%	58%	65%	64%	67%	62%	71%	68%	71%
fft8	0%	0%	12%	13%	13%	29%	19%	25%	24%	32%	38%	37%
fftRadix4	0%	0%	−1%	15%	21%	29%	21%	39%	28%	43%	32%	43%
fft16	0%	0%	16%	28%	9%	18%	11%	25%	−10%	5%	18%	27%
linjacobi	27%	28%	50%	52%	47%	59%	61%	67%	63%	68%	62%	70%
linsor	65%	69%	68%	68%	70%	72%	70%	72%	71%	72%	70%	74%
conv9x9	19%	19%	50%	50%	66%	70%	69%	74%	76%	78%	75%	80%
Average	14%	15%	27%	31%	32%	41%	35%	42%	35%	41%	40%	45%
small0	1%	1%	1%	1%	10%	13%	10%	13%	2%	11%	48%	57%
small1	0%	1%	0%	1%	0%	1%	3%	30%	3%	30%	2%	4%
small2	0%	0%	0%	0%	20%	22%	20%	22%	19%	30%	39%	40%
small3	30%	30%	30%	30%	57%	57%	53%	57%	45%	58%	58%	57%
small4	30%	49%	30%	49%	38%	38%	49%	57%	40%	49%	57%	57%
small5	27%	44%	35%	54%	37%	45%	28%	30%	38%	39%	45%	46%
small6	5%	5%	5%	5%	11%	20%	29%	38%	29%	28%	31%	49%
small7	0%	0%	0%	0%	31%	35%	39%	47%	50%	57%	54%	58%
medium0	3%	3%	37%	42%	50%	52%	50%	55%	57%	61%	52%	60%
medium1	3%	3%	32%	44%	49%	54%	51%	55%	58%	62%	60%	64%
medium2	0%	0%	38%	42%	51%	54%	58%	63%	60%	63%	62%	67%
medium3	6%	6%	33%	39%	45%	50%	49%	55%	52%	57%	52%	59%
medium4	0%	0%	33%	37%	43%	51%	49%	51%	52%	57%	57%	60%
Average	8%	11%	21%	27%	34%	38%	37%	44%	39%	46%	48%	52%
Total average	11%	13%	24%	28%	33%	39%	37%	43%	37%	44%	45%	49%