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International Journal of Reconfigurable Computing
Volume 2017, Article ID 6817674, 11 pages
https://doi.org/10.1155/2017/6817674
Research Article

OpenCL-Based FPGA Accelerator for 3D FDTD with Periodic and Absorbing Boundary Conditions

1Graduate School of Information Sciences, Tohoku University, Aoba 6-3-09, Aramaki-Aza-Aoba, Sendai, Miyagi 980-8579, Japan
2Graduate School of Information Sciences, Tohoku University, Aoba 6-3-05, Aramaki-Aza-Aoba, Sendai, Miyagi 980-8579, Japan

Correspondence should be addressed to Hasitha Muthumala Waidyasooriya; pj.ca.ukohot.iece@ahtisah

Received 22 December 2016; Revised 3 March 2017; Accepted 30 March 2017; Published 16 April 2017

Academic Editor: João Cardoso

Copyright © 2017 Hasitha Muthumala Waidyasooriya et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Citations to this Article [3 citations]

The following is the list of published articles that have cited the current article.

  • Li Luo, Yakun Wu, Fei Qiao, Yi Yang, Qi Wei, Xiaobo Zhou, Yongkai Fan, Shuzheng Xu, Xinjun Liu, and Huazhong Yang, “Design of FPGA-Based Accelerator for Convolutional Neural Network under Heterogeneous Computing Framework with OpenCL,” International Journal of Reconfigurable Computing, vol. 2018, pp. 1–10, 2018. View at Publisher · View at Google Scholar
  • Stefan Pijetlovic, Milos Subotic, and Nebojsa Pjevalica, “Optimizing FDTD memory bandwidth by using block float-point arithmetic,” Elektronika ir Elektrotechnika, vol. 24, no. 4, pp. 32–37, 2018. View at Publisher · View at Google Scholar
  • Hasitha Muthumala Waidyasooriya, and Masanori Hariyama, “Multi-FPGA Accelerator Architecture for Stencil Computation Exploiting Spacial and Temporal Scalability,” IEEE Access, vol. 7, pp. 53188–53201, 2019. View at Publisher · View at Google Scholar