Table 1: Comparison of the FPGA accelerators with different data access methods using DE5 board.

MethodProcessing time (s)Area (%)Frequency (MHz)
ALMsRegistersMemory (kByte)DSPsRAM blocks

Noncoalesced (36 bytes/cell)8.01179,925 (77)368,483 (39)2,911 (45)114 (45)2,050 (80)205.6
Coalesced (36 bytes/cell, nonaligned)14.75176,370 (75)357,220 (38)3,012 (47)114 (45)1,953 (76)206.7
Coalesced (36 bytes/cell, aligned)9.42170,692 (73)349,960 (37)2,958 (45)114 (45)1,879 (73)217.8
Coalesced (32 bytes/cell, aligned)6.31175,032 (75)357,283 (38)2,595 (41)114 (45)1,750 (68)260.0
Coalesced (28 bytes/cell, aligned)6.69176,637 (75)359,472 (38)2,363 (36)114 (45)1,618 (63)243.6