OpenCL-Based FPGA Accelerator for 3D FDTD with Periodic and Absorbing Boundary Conditions

Table 4

Comparison with other FPGA accelerators for 3D FDTD with boundary conditions.

Method	Boundary conditions	FPGA	Performance; mega cell/s	Clock frequency MHz	Achieved throughput (maximum bandwidth) GB/s
Work in [9]	ABC	n/a	1,000	50	n/a
Work in [5]	fixed	Xilinx Virtex-6 XC6VSX475T	325	100	n/a
Work in [10]	fixed		1,820		26.8 (38.6)
	fixed and ABC	Xilinx Virtex-6 XC6VSX475T 4	1,193	100	29.9 (38.6)
	ABC and PBC		100		n/a
This paper	ABC and PBC	Altera Stratix-V 5SGXEA7N2F45C2	1,427	260	13.4 (25.6)

n/a: not available.