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International Journal of Reconfigurable Computing
Volume 2017 (2017), Article ID 7021056, 9 pages
Research Article

Exploring Shared SRAM Tables in FPGAs for Larger LUTs and Higher Degree of Sharing

1Karachi Institute of Economics and Technology, Karachi, Pakistan
2Umm Al-Qura University, Makkah, Saudi Arabia

Correspondence should be addressed to Ali Asghar; moc.liamg@98rahgsaila

Received 8 January 2017; Accepted 23 April 2017; Published 13 June 2017

Academic Editor: Seda Ogrenci-Memik

Copyright © 2017 Ali Asghar et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


In modern SRAM based Field Programmable Gate Arrays, a Look-Up Table (LUT) is the principal constituent logic element which can realize every possible Boolean function. However, this flexibility of LUTs comes with a heavy area penalty. A part of this area overhead comes from the increased amount of configuration memory which rises exponentially as the LUT size increases. In this paper, we first present a detailed analysis of a previously proposed FPGA architecture which allows sharing of LUTs memory (SRAM) tables among NPN-equivalent functions, to reduce the area as well as the number of configuration bits. We then propose several methods to improve the existing architecture. A new clustering technique has been proposed which packs NPN-equivalent functions together inside a Configurable Logic Block (CLB). We also make use of a recently proposed high performance Boolean matching algorithm to perform NPN classification. To enhance area savings further, we evaluate the feasibility of more than two LUTs sharing the same SRAM table. Consequently, this work explores the SRAM table sharing approach for a range of LUT sizes (4–7), while varying the cluster sizes (4–16). Experimental results on MCNC benchmark circuits set show an overall area reduction of ~7% while maintaining the same critical path delay.