Algorithm and Architecture Optimization for 2D Discrete Fourier Transforms with Simultaneous Edge Artifact Removal

<table class="figure-group"><tr class="fig-image" id="a"><td><object data="https://static.hindawi.com/articles/ijrc/volume-2018/1403181/figures/1403181.fig.006a.svgz" name="1403181.fig.006a" type="image/svg+xml"></object></td></tr><tr class="fig-caption"><td><b>(a) </b>Dataset view</td></tr><tr class="fig-image" id="b"><td><object data="https://static.hindawi.com/articles/ijrc/volume-2018/1403181/figures/1403181.fig.006b.svgz" name="1403181.fig.006b" type="image/svg+xml"></object></td></tr><tr class="fig-caption"><td><b>(b) </b>Memory view</td></tr><tr class="fig-image" id="c"><td><object data="https://static.hindawi.com/articles/ijrc/volume-2018/1403181/figures/1403181.fig.006c.svgz" name="1403181.fig.006c" type="image/svg+xml"></object></td></tr><tr class="fig-caption"><td><b>(c) </b>Memory view</td></tr></table>

<div>Image showing tile-hopping. (a) Image-level view showing tiles. (b) DRAM-level view showing tile placement while writing. (c) DRAM-level view showing column reading from the tiles.</div>

International Journal of Reconfigurable Computing

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Figure 6

Figure 6: Algorithm and Architecture Optimization for 2D Discrete Fourier Transforms with Simultaneous Edge Artifact Removal 