Research Article
Design of FPGA-Based Accelerator for Convolutional Neural Network under Heterogeneous Computing Framework with OpenCL
Table 5
The optimization results.
| Optimization Methods | FFs | LUTs | DSPs | Block RAMs | Time(ms) |
| Baseline | 5360 | 8793 | 16 | 18 | 50.4 |
| Loop Pipeline | 5374 | 8814 | 16 | 18 | 50.0 |
| Loop Unroll | 5533 | 10214 | 16 | 18 | 27.9 |
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