Research Article
On a Real-Time Blind Signal Separation Noise Reduction System
Table 4
Maximum speedup with multiple instances in the FPGA device.
| | Samples/s | Number of Instances | Slices | DSP | | FFT / IFFT | Complex Matrix Multiplier | Used | Used |
| | | 1 | 1 | 24% | 14% |
| | | 1 | 2 | 37% | 24% |
| | | 1 | 3 | 50% | 33% |
| | | 1 | 4 | 63% | 42% |
| | | 1 | 5 | 73% | 52% |
| | | 1 | 6 | 86% | 61% |
| | | 2 | 1 | 35% | 18% |
| | | 2 | 2 | 48% | 27% |
| | | 2 | 3 | 61% | 35% |
| | | 2 | 4 | 74% | 46% |
| | | 2 | 5 | 87% | 53% |
| | | 3 | 1 | 46% | 22% |
| | | 3 | 2 | 59% | 31% |
| | | 3 | 3 | 72% | 40% |
| | | 3 | 4 | 85% | 49% |
| | | 4 | 1 | 57% | 26% |
| | | 4 | 2 | 70% | 34% |
| | | 4 | 3 | 83% | 43% |
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