FPGA Implementation of Reconfigurable Finite State Machine with Input Multiplexing Architecture Using Hungarian Method

Algorithm 1

Iterative greedy heuristic based Hungarian algorithm.

Input. The descriptions of the FSMs (i.e. )

Output. The optimized multiplexer bank for mode based reconfiguration

begin

select the largest FSM from the set based on the description;

base_ckt ← largest FSM;

← rest of the FSMs in the set;

for each recon_ckt_b∈ do

if (L_base ≥ L_recon) then performing the input matching

generate, combinations_of_input_lines for base_ckt to match with

input lines of recon_ckt_b;

go to state_matching; calling the function- “state_matching”

else if then

generate, combinations_of_input_lines for recon_ckt_b to match

with input lines of base_ckt;

go to state_matching; calling the function- “state_matching”

end

select combinations_of_input_lines with

& ;

perform binary state assignment in base_ckt & recon_ckt_b i.e. apply   &  ;

weight_assignment( ); creating arrays by [selected_input_combination, , ]

go to dummy_replacement; calling the function- “dummy_replacement”

if (_base ≥ _recon) then performing the output matching

generate, combinations_of_output_lines for base_ckt to match

with output lines of recon_ckt_b;

go to output_matching; calling the function- “output_matching”

else if then

generate, combinations_of_output_lines for recon_ckt_b to match

with output lines of base_ckt;

go to output_matching; calling the function- “output_matching”

end

select combinations_of_output_lines with ;

update the description of base_ckt;

end

for each recon_ckt_b∈ do

go to dummy_replacement; calling the function- “dummy_replacement”

update the description of recon_ckt_b;

end

perform a mutual (i.e. ) Bitwise-XOR operations between the updated descriptions of FSMs;

obtain the optimized multiplexer bank for mode based reconfiguration;

end