Research Article
SIFO: Secure Computational Infrastructure Using FPGA Overlays
Table 1
Gate information for problems.
| Problem | Layers | Input wires | Output wires | ANDs | XORs | Gates | # Reprogram |
| 6 bit adder | 17 | 12 | 6 | 6 | 24 | 30 | 1 | 10 bit HD | 22 | 20 | 10 | 20 | 90 | 110 | 1 | 30 bit HD | 27 | 60 | 30 | 60 | 270 | 330 | 6 | 50 bit HD | 32 | 100 | 50 | 100 | 450 | 550 | 10 | 8 bit mult | 57 | 16 | 16 | 120 | 352 | 472 | 12 | 16 bit mult | 121 | 32 | 32 | 496 | 1472 | 1968 | 50 | 32 bit mult | 249 | 64 | 64 | 2016 | 6016 | 8032 | 201 | 64 bit mult | 505 | 128 | 128 | 8128 | 24320 | 32448 | 813 | 10 4 bit sorting | 278 | 40 | 40 | 848 | 4638 | 5486 | 85 | 4 bit m_mult | 25 | 100 | 200 | 3900 | 11600 | 15500 | 390 | 4 bit m_mult | 27 | 400 | 800 | 7526 | 22489 | 30015 | 753 | 8 bit m_mult | 57 | 200 | 400 | 15800 | 47200 | 63000 | 1580 | 8 bit m_mult | 57 | 800 | 1600 | 127200 | 380800 | 508000 | 12720 | 4 bit m_mult | 37 | 1600 | 3200 | 254400 | 761600 | 1016000 | 25440 |
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