International Journal of Reconfigurable Computing / 2019 / Article / Tab 11

Research Article

SIFO: Secure Computational Infrastructure Using FPGA Overlays

Table 11

Speedup results.

ProblemSw (ms)Time (µs)Speedup

6 bit adder2.064545.78
10 bit HD2.538031.63
30 bit HD4.0817123.86
50 bit HD6.4625924.94
8 bit mult9.2229331.47
16 bit mult14.5494915.32
32 bit mult33.76330810.21
64 bit mult153.131225212.50
10 4 bit sort21.1223399.03
4 bit m_mult60.66583010.40
4 bit m_mult220.811128619.56
8 bit m_mult203.86241288.45
8 bit m_mult1060.631708956.21
4 bit m_mult2170.883406986.37

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