SIFO: Secure Computational Infrastructure Using FPGA Overlays

Table 4

Wire percent for problems.

Problem	Percent A (%)	Percent B (%)	Percent C (%)
6 bit adder	28.57	100.0	28.6
10 bit HD	39.29	90.9	35.7
30 bit HD	35.00	90.2	38.8
50 bit HD	41.86	91.8	38.4
8 bit mult	59.80	83.4	49.9
16 bit mult	61.14	81.7	50.0
32 bit mult	61.82	80.9	50.0
64 bit mult	62.16	80.4	50.0
10 4 bit sorting	51.92	72.0	37.4
4 bit m_mult	59.97	86.1	51.6
4 bit m_mult	59.63	85.5	51.0
8 bit m_mult	61.20	83.4	51.0
8 bit m_mult	61.37	82.9	50.9
4 bit m_mult	60.45	85.3	51.5

Percent A: percent of 1-to-1 wire in all wires; percent B: 1-to-1 wires to be used in the next layer of all 1-to-1 wires; percent C: 1-to-1 wires to be used in the next layer of all wires.