SIFO: Secure Computational Infrastructure Using FPGA Overlays

Table 5

Increase number of AND overlay cells.

Problem	5 AND overlay (µs)	Speedup	10 AND overlay (µs)	Total speedup
6 bit adder	78	26.41	76	27.11
10 bit HD	260	9.73	257	9.84
30 bit HD	765	5.33	741	5.51
50 bit HD	1282	5.04	1210	5.34
8 bit mult	1098	8.40	1058	8.71
16 bit mult	4280	3.40	4218	3.45
32 bit mult	17406	1.94	17056	1.98
64 bit mult	71068	2.15	69858	2.19
10 4 bit sorting	12605	1.68	12375	1.71