International Journal of Reconfigurable Computing / 2019 / Article / Tab 5

Research Article

SIFO: Secure Computational Infrastructure Using FPGA Overlays

Table 5

Increase number of AND overlay cells.

Problem5 AND overlay (µs)Speedup10 AND overlay (µs)Total speedup

6 bit adder7826.417627.11
10 bit HD2609.732579.84
30 bit HD7655.337415.51
50 bit HD12825.0412105.34
8 bit mult10988.4010588.71
16 bit mult42803.4042183.45
32 bit mult174061.94170561.98
64 bit mult710682.15698582.19
10 4 bit sorting126051.68123751.71

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