Research Article
SIFO: Secure Computational Infrastructure Using FPGA Overlays
Table 6
Results for removing host XOR operation check.
| Problem | 10 AND w/o XOR check (µs) | Additional speedup | Total speedup |
| 6 bit adder | 60 | 1.30 | 34.33 | 10 bit HD | 99 | 2.63 | 25.56 | 30 bit HD | 216 | 3.43 | 18.89 | 50 bit HD | 365 | 3.32 | 17.70 | 8 bit mult | 428 | 2.47 | 21.54 | 16 bit mult | 1420 | 2.97 | 10.24 | 32 bit mult | 4924 | 3.46 | 6.86 | 64 bit mult | 18673 | 3.74 | 8.20 | 10 4 bit sorting | 2770 | 4.47 | 7.62 |
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