International Journal of Reconfigurable Computing / 2019 / Article / Tab 6

Research Article

SIFO: Secure Computational Infrastructure Using FPGA Overlays

Table 6

Results for removing host XOR operation check.

Problem10 AND w/o XOR check (µs)Additional speedupTotal speedup

6 bit adder601.3034.33
10 bit HD992.6325.56
30 bit HD2163.4318.89
50 bit HD3653.3217.70
8 bit mult4282.4721.54
16 bit mult14202.9710.24
32 bit mult49243.466.86
64 bit mult186733.748.20
10 4 bit sorting27704.477.62

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